View AD5725BRSZ-500RL7_4552502.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

quad, 12-bit, parallel input, unipolar/bipolar, voltage output dac ad5725 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2008 analog devices, inc. all rights reserved. features +5 v to 15 v operation unipolar or bipolar operation 0.5 lsb max inl error, 1 lsb max dnl error settling time: 10 s max (10 v step) double-buffered inputs simultaneous updating via ldac asynchronous clr to zero/mid scale readback operating temperature range: ?40c to +85c i cmos ? process technology applications industrial automation closed-loop servo control, process control automotive test and measurement programmable logic controllers functional block diagram dac c dac d dac b dac a dgnd ad5725 12 v out a 12 v outb 12 v outc 12 v outd 12 12 i/o register and control logic v refp a v dd a v ss v l a0 a1 r/w cs db0 to db11 v refn ldac clr input reg a input reg b input reg c input reg d dac reg a dac reg b dac reg c dac reg d 06442-001 figure 1. general description the ad5725 is a quad, 12-bit, parallel input, voltage output digital-to-analog converter that offers guaranteed monotonicity, integral nonlinearity (inl) of 0.5 lsb maximum and 10 s maximum settling time. output voltage swing is set by two reference inputs, v refp and v refn . by setting the v refn input to 0 v and the v refp to a positive voltage, the dac provides a unipolar positive output range. a similar configuration with v refp at 0 v and v refn at a negative voltage provides a unipolar negative output range. bipolar outputs are configured by connecting both v refp and v refn to nonzero voltages. this method of setting output voltage ranges has advantages over the bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. digital controls allow the user to load or read back data from any dac, load any dac, and transfer data to all dacs at one time. the ad5725 is available in a 28-lead ssop package. it can be operated from a wide variety of supply and reference voltages, with supplies ranging from single +5 v to 15 v, and references from +2.5 v to 10 v. power dissipation is less than 270 mw with 15 v supplies and only 40 mw with a +5 v supply. operation is specified over the temperature range of ?40c to +85c. i cmos? process technology for analog systems designers within industrial/instrumentation equipment oems who need high performance ics at higher-voltage l evels, i cmos is a technology platform that enables the development of analog ics capable of 30 v and operating at 15 v supplies while allowing dramatic red uctions in power consumption and package size, and increased ac and dc performance.
ad5725 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac performance characteristics ................................................ 5 ? timing characteristics , ............................................................... 6 ? absolute maximum ratings ............................................................ 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 14 ? theory of operation ...................................................................... 15 ? dac architecture ....................................................................... 15 ? output amplifiers ...................................................................... 15 ? reference inputs ......................................................................... 15 ? parallel interface ......................................................................... 15 ? data coding ................................................................................ 15 ? clr .............................................................................................. 15 ? power supplies ............................................................................ 17 ? reference configuration ........................................................... 17 ? single +5 v supply operation .................................................. 18 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 19 ? revision history 12/08rev. 0 to rev. a changes to figure 26 ...................................................................... 13 7/07revision 0: initial version
ad5725 rev. a | page 3 of 20 specifications av dd = +15 v, av ss = ?15 v, dgnd = 0 v; v refp = +10 v; v refn = ?10 v, v l = 5 v. all specifications t min to t max , unless otherwise noted. 1 table 1. parameter value unit test conditions/comments accuracy outputs unloaded resolution 12 bits relative accuracy (inl) 0.5 lsb max b grade 1 lsb max a grade differential nonlinearity (dnl) 1 lsb max guaranteed monotonic zero-scale error 2 lsb max r l = 2 k zero-scale tc 2 15 ppm fsr/c typ r l = 2 k full-scale error 2 lsb max r l = 2 k full-scale tc 2 20 ppm fsr/c typ r l = 2 k reference input v refp reference input range 3 v refn + 2.5 v min av dd ? 2.5 v max input current 2.75 ma max typically 1.5 ma v refn reference input range 3 ?10 v min v refp ? 2.5 v max input current 2 2.75 ma max typically 2 ma large signal bandwidth 2 160 khz typ ?3 db, v refp = 0 v to 10 v p-p output characteristics 2 output current 5 ma max r l = 2 k, c l = 100 pf digital inputs v l = 2.7 v to 5.5 v, jedec compliant v ih , input high voltage 2.4 v min t a = 25c v il , input low voltage 0.8 v max t a = 25c input current 2 1 a max input capacitance 2 8 pf typ digital outputs (sdo) v oh , output high voltage 4 v min i oh = 0.4 ma v ol , output low voltage 0.4 v max i ol = ?1.6 ma power supply characteristics power supply sensitivity 2 30 ppm fsr/v max 14.25 v av dd 15.75 v ai dd 3 ma/channel max outputs unloaded, v refp = 2.5 v, typically 2.125 ma ai ss 2.5 ma/channel max outputs unloaded, typically 1.625 ma power dissipation 270 mw max 1 all supplies can be varied 5%, and operation is guaranteed. device is tested with nominal supplies. 2 guaranteed by design and characterization, not production tested. 3 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
ad5725 rev. a | page 4 of 20 av dd = +5 v, av ss = ?5 v/0 v, dgnd = 0 v; v refp = +2.5 v; v refn = ?2.5 v/0 v, v l = 5 v. all specifications t min to t max , unless otherwise noted. table 2. parameter value unit test conditions/comments accuracy outputs unloaded resolution 12 bits relative accuracy (inl) 0.5 lsb max b grade 1 lsb max a grade 1 lsb max b grade, av ss = 0 v 1 2 lsb max a grade, av ss = 0 v 1 differential nonlinearity (dnl) 1 lsb max guaranteed monotonic zero-scale error 5 lsb max av ss = ?5 v 10 lsb max av ss = 0 v zero-scale tc 2 100 ppm fsr/c typ full-scale error 5 lsb max av ss = ?5 v 10 lsb max av ss = 0 v full-scale tc 2 100 ppm fsr/c typ reference input v refp reference input range 3 v refn + 2.5 v min av dd ? 2.5 v max input current 2 0.5 ma max code 0x0000 v refn reference input range 3 ?2.5 v min av ss = ?5 v 0 v min av ss = 0 v v refp ? 2.5 v max large signal bandwidth 2 450 khz typ ?3 db, v refp = 0 v to 2.5 v p-p output characteristics 2 output current 1.25 ma max r l = 2 k, c l = 100 pf digital inputs v l = 2.7 v to 5.5 v, jedec compliant v ih , input high voltage 2.4 v min t a = 25c v il , input low voltage 0.8 v max t a = 25c input current 2 1 a max input capacitance 2 8 pf typ digital outputs (sdo) v oh , output high voltage 4 v min i oh = 0.4 ma v ol , output low voltage 0.4 v max i ol = ?1.6 ma power supply characteristics power supply sensitivity 2 100 ppm fsr/v typ ai dd 2 ma/channel max outputs unloaded. ai ss 1.5 ma/channel max outputs unloaded, a vss = ?5 v power dissipation 70 mw max av ss = ?5 v 40 mw max av ss = 0 v 1 for single supply operation only (v refn = 0 v, av ss = 0 v): due to internal offs et errors, inl and dnl are meas ured beginning at code 0x005. 2 guaranteed by design and characterization, not production tested. 3 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
ad5725 rev. a | page 5 of 20 ac performance characteristics 1 av dd = +15 v/+5 v, av ss = ?15 v/?5 v/0 v, dgnd = 0 v; v refp = +10 v/+2.5 v; v refn = ?10 v/?2.5 v/0 v, v l = 5 v. all specifications t min to t max , unless otherwise noted. table 3. parameter a grade b grade unit test conditions/comments dynamic performance output voltage settling time 10 10 s typ to 0.01%, 10 v step, r l = 1 k 7 7 s typ to 0.01%, 2.5 v step, r l = 1 k slew rate 2.2 2.2 v/s typ 10% to 90% analog crosstalk 72 72 db typ digital feedthrough 5 5 nv-s typ 1 guaranteed by design and characterization, not production tested.
ad5725 rev. a | page 6 of 20 timing characteristics 1 , 2 av dd = +5 v/+15 v, av ss = ?5 v/0 v/?15 v, dgnd = 0 v; v refp = +2.5 v/+10 v; v refn = ?2.5 v/0 v/?10 v, v l = 5 v. all specifications t min to t max , unless otherwise noted. table 4. parameter limit at t min , t max unit description t wcs 10 ns min chip select write pulse width t ws 0 ns min write setup, t wcs = 10 ns t wh 0 ns min write hold, t wcs = 10 ns t as 0 ns min address setup t ah 0 ns min address hold t ls 5 ns min load setup t lh 5 ns min load hold t wds 5 ns min write data setup, t wcs = 10 ns t wdh 0 ns min write data hold, t wcs = 10 ns t ldw 10 ns min load data pulse width t reset 10 ns min reset pulse width t rcs 30 ns min chip select read pulse width t rdh 0 ns min read data hold, t rcs = 30 ns t rds 0 ns min read data setup, t rcs = 30 ns t dz 15 ns max data to high-z, c l = 10 pf t csd 35 ns max chip select to data, c l = 100 pf 1 all input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 2 guaranteed by design and characterization, not production tested.
ad5725 rev. a | page 7 of 20 timing diagrams a0/a1 data out t dz t rcs t rds t rdh t as t ah t csd cs r/w high-z high-z data valid 0 6442-002 figure 2. data read timing a0/a1 data in t wcs t ws t wh t ah t as t ls t wds t wdh t ldw t reset t lh r/w cs ldac reset 06442-003 figure 3. data write timing address 10ns t ws t as t ls t wds data1 valid data2 valid data3 valid data4 valid t wdh t lh t wh address two address three data in ldac r/w cs address four address one 06442-004 figure 4. single buffer mode timing address 10ns t ws t as t ls t wds data1 valid data2 valid data3 valid data4 valid t wdh t lh t wh address two address three t ldw data in ldac cs r/w address four address one 06442-005 figure 5. double buffer mode timing
ad5725 rev. a | page 8 of 20 absolute maximum ratings t a = 25c unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 5. parameter rating av ss to dgnd +0.3 v to ?16.5 v av dd to dgnd ?0.3 v to +16.5 v av ss to av dd +0.3 v to ?33 v v l to dgnd ?0.3 v to +7 v current into any pin 15 ma digital pin voltage to dgnd ?0.3 v to +7 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 105c 28-lead ssop package ja thermal impedance 100c/w jc thermal impedance 39c/w power dissipation package (derate 10 mw/c above 70c) 900 mw reflow soldering time at peak temperature 10 sec to 40 sec lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5725 rev. a | page 9 of 20 pin configuration and fu nction descriptions v refp 1 v outb 2 v outa 3 av ss 4 v refn 28 v outc 27 v outd 26 av dd 25 dgnd 5 clr 6 ldac 7 v l 24 cs 23 a0 22 db0 (lsb) 8 a1 21 db1 9 r/w 20 db2 10 db11 (msb) 19 db3 11 db10 18 db4 12 db9 17 db5 13 db8 16 db6 14 db7 15 ad5725 top view (not to scale) 0 6442-006 figure 6. pin configuration diagram table 6. pin function descriptions pin no. mnemonic description 1 v refp positive dac reference input. the voltage applied to this pin defines the full-scale output voltage. allowable range is av dd ? 2.5 v to v refn + 2.5 v. 2 v outb buffered analog output voltage of dac b. 3 v outa buffered analog output voltage of dac a. 4 av ss negative analog supply pin. voltage ranges from 0 v to ?15 v. 5 dgnd digital ground pin. 6 clr active low input. sets input registers and dac regi sters to zero scale (0x000) for the ad5725-1 or midscale (0x800) for the ad5725. 7 ldac active low load dac input. 8 db0 data bit 0 (lsb). 9 db1 data bit 1. 10 db2 data bit 2. 11 db3 data bit 3. 12 db4 data bit 4. 13 db5 data bit 5. 14 db6 data bit 6. 15 db7 data bit 7. 16 db8 data bit 8. 17 db9 data bit 9. 18 db10 data bit 10. 19 db11 data bit 11 (msb). 20 r/ w read/write pin. active low to write data to dac; active high to read back previous data at data bit pins with v l connected to +5 v. 21 a1 address bit 1. 22 a0 address bit 0. 23 cs active low chip select pin. 24 v l voltage supply for readback function. can be left open circuit if not used. 25 av dd positive analog supply pin. voltage ranges from +5 v to +15 v. 26 v outd buffered analog output voltage of dac d. 27 v outc buffered analog output voltage of dac c. 28 v refn negative dac reference input. the voltage applied to this pin defines the zero-scale output voltage. allowable range is av ss to v refp ? 2.5 v.
ad5725 rev. a | page 10 of 20 typical performance characteristics 1.0 ?1.0 61 2 v refp (v) max dnl error (lsb) av dd = +15v av ss = ?15v v refn = ?10v t a = 25c 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 7891011 06442-017 figure 7. dnl vs. v refp (v supply = 15 v) 0.05 ?0.25 1.0 3.0 v refp (v) max dnl error (lsb) 0 ?0.05 ?0.10 ?0.15 ?0.20 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 av dd = 5v av ss = 0v v refn = 0v t a = 25c 06442-018 figure 8. dnl vs. v refp (v supply = +5 v) 1.0 ?1.0 61 2 v refp (v) max inl error (lsb) av dd = +15v av ss = ?15v v refn = ?10v t a = 25c 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 7 8 9 10 11 06442-019 figure 9. inl vs. v refp (v supply = 15 v) 0.5 ?0.4 1.0 3.0 v refp (v) max inl error (lsb) 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 av dd = 5v av ss = 0v v refn = 0v t a = 25c 06442-020 figure 10. inl vs. v refp (v supply = +5 v) 0 ?0.7 ?40 80 temperature (c) full-scale error (lsb) ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?20 0 20 40 60 dac d dac c dac a dac b av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v 2k? load 06442-023 figure 11. full-scale error vs. temperature 0.3 ?0.3 ?40 80 temperature (c) zero-scale error (lsb) 0.2 0.1 0 ?0.1 ?0.2 ?20 0 20 40 60 dac a dac d dac b dac c av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v 2k ? load 06442-024 figure 12. zero-scale error vs. temperature
ad5725 rev. a | page 11 of 20 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 0 500 1000 1500 2000 2500 3000 3500 4000 dac (code) inl error (lsb) dac a dac b dac c dac d av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v t a = 25c 06442-025 figure 13. channel-to-channel matching (v supply = 15 v) 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 0 500 1000 1500 2000 2500 3000 3500 4000 dac (code) inl error (lsb) av dd = 5v av ss = 0v v refp = 2.5v v refn = 0v t a = 25c dac a dac b dac c dac d 06442-026 figure 14. channel-to-channel matching (v supply = +5 v) 16 0 ?7 13 v refp (v) i dd (ma) 14 12 10 8 6 4 2 ?5?3?11357911 av dd = +15v av ss = ?15v v refn = ?10v digital inputs high t a = 25c 06442-027 figure 15. i dd vs. v refp 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 0 500 1000 1500 2000 2500 3000 3500 4000 dac (code) inl error (lsb) +85c +25c ?40c 06442-028 av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v figure 16. inl vs. dac code 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 dac (code) dnl error (lsb) +85c +25c ?40c av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 06442-042 figure 17. dnl vs. dac code 1.7995 ?0.0005 0 4000 dac (code) iv refp (ma) 1.5995 1.3995 1.1995 0.9995 0.7995 0.5995 0.3995 0.1995 500 1000 1500 2000 2500 3000 3500 v refp = +10v v refn = ?10v t a = 25c av dd = +15v av ss = ?15v 06442-029 figure 18. iv refp vs. dac code
ad5725 rev. a | page 12 of 20 12 0 0.01 100 load resistance (k ? ) full-scale voltage (v) 0.1 1 10 10 8 6 4 2 av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v t a = 25c 06442-035 figure 19. output voltage swing vs. resistive load 2 ?16 10 10m frequency (hz) gain (db) 100 1k 10k 100k 1m 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 av dd = +15v av ss = ?15v v refp = 0v 100mv v refn = ?10v data bits = +5v t a = 25c 06442-036 figure 20. small signal response 8 ?8 ?35 85 temperature (c) power supply current (ma) 6 4 2 0 ?2 ?4 ?6 ?15 5 25 45 65 i dd i ss av dd = +15v av ss = ?15v 06442-045 figure 21. power supply current vs. temperature 1.0 ?0.1 1 100k noise frequency (hz) noise density (mv) 10 100 1k 10k 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v t a = 25c 06442-044 figure 22. output noise spec tral density vs. frequency 20 ?20 ?15 15 v out (v) i out (a) 15 10 5 0 ?5 ?10 ?15 ?10 ?5 0 5 10 av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v t a = 25c data = 0x000 06442-040 figure 23. i out vs. v out (v supply = 15 v) 25 ?10 01 v out (v) i out (a) 0 20 15 10 5 0 ?5 123456789 av dd = 15v av ss = 0v v refp = 10v v refn = 0v t a = 25c data = 0x800 06442-041 figure 24. i out vs. v out (v supply = +15 v)
ad5725 rev. a | page 13 of 20 ch1 50v m 2s a ch1 0v 1 av dd = +15v av ss = ?15v v refp = +10v v refn = ?10v t a = 25c bw = 100khz 06442-046 figure 25. broadband noise 06442-043 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 0 1000900800700600 500 400300200100 time (ns) glitch amplitude (v) 0x800 0x7ff (15v supply) 0x7ff 0x800 (15v supply) 0x800 0x7ff (5v supply) 0x7ff 0x800 (5v supply) figure 26. output glitch
ad5725 rev. a | page 14 of 20 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 16 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 17 . monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5725 is monotonic over its full operating temperature range. full-scale error full-scale error is a measure of the output error when full-scale code is loaded to the dac register. ideally, the output should be v refp ? 1 lsb. full-scale error is expressed in lsbs. a plot of full-scale error vs. temperature can be seen in figure 11 . full-scale error tc full-scale error tc is a measure of the change in full-scale error with a change in temperature. full-scale error tc is expressed in ppm fsr/c. zero-scale error zero-scale error is the error in the dac output voltage when 0x0000 (straight binary coding) is loaded to the dac register. ideally, the output voltage should be v refn . a plot of zero-scale error vs. temperature can be seen in figure 12 . zero-scale error tc zero-scale error tc is a measure of the change in zero-scale error with a change in temperature. zero-scale error tc is expressed in ppm fsr/c. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed of a voltage- output dac is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but it is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus. power supply sensitivity power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage. analog crosstalk analog crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in db.
ad5725 rev. a | page 15 of 20 theory of operation the ad5725 is a quad voltage output, 12-bit parallel input dac featuring a 12-bit data bus with readback capability. the ad5725 operates from single or dual supplies ranging from +5 v up to 15 v. the output voltage range is set by the reference voltages applied at the v refp and v refn pins. dac architecture each of the four dacs is a voltage switched, high impedance (50 k), r-2r ladder configuration. each 2r resistor is driven by a pair of switches that connect the resistor to either v refh or v refl . output amplifiers the output amplifiers are capable of generating both unipolar and bipolar output voltages. they are capable of driving a load of 2 k in parallel with 500 pf to dgnd. the source and sink capabilities of the output amplifiers can be seen in figure 23 and figure 24 . the slew rate is 2.2 v/s with a full-scale settling time of 10 s. the amplifiers are short-circuit protected. careful attention to grounding is important for accurate operation of the ad5725. with four outputs and two references there is potential for ground loops. since the ad5725 has no analog ground, the ground must be specified with respect to the reference. reference inputs all four dacs share common positive reference (v refp ) and negative reference (v refn ) inputs. the voltages applied to these reference inputs set the output high and low voltage limits on all four of the dacs. each reference input has voltage restrictions with respect to the other reference and to the power supplies. v refn can be any voltage between av ss and v refp ? 2.5 v and v refp can be any value between av dd C 2.5 v and v refn + 2.5 v. note that because of these restrictions, the ad5725 references cannot be inverted (v refn cannot be greater than v refp ). it is important to note that the ad5725 v refp input both sinks and sources current. also, the input current of both v refp and v refn are code dependent. many references have limited current sinking capability and must be buffered with an amplifier to drive v refp . the v refn reference input has no such special requirements. it is recommended that the reference inputs be bypassed with 0.2 f capacitors when operating with 10 v references. this limits the reference bandwidth. parallel interface see table 7 for the digital control logic truth table. the parallel interface consists of a 12-bit bidirectional data bus, two register select inputs, a0 and a1, a r/ w input, a chip select ( cs ), and a load dac ( ldac ) input. control of the dacs and bus direction is determined by these inputs as shown in . digital data bits are labeled with the msb defined as data bit 11 and the lsb as data bit 0. all digital pins are ttl/cmos compatible. table 7 the register select inputs a0 and a1 select individual dac register a (binary code 00) through register d (binary code 11). decoding of the registers is enabled by the cs input. when cs is high, no decoding takes place, and neither the writing nor the reading of the input registers is enabled. the loading of the second bank of registers is controlled by the asynchronous ldac input. by taking ldac low while cs is high, all output registers can be updated simultaneously. note that the t ldw required pulse width for updating all dacs is a minimum of 10 ns. the r/ w input, when enabled by cs , controls the writing to and reading from the input register. data coding the ad5725 uses binary coding. the output voltage can be calculated as follows: ( ) 4096 dvv vv refn refp refn out ? += where d is the digital code in decimal. clr the clr function can be used either at power-up or at any time during the dacs operation. the clr function is independent of cs . this pin is active low and sets the dac registers to either midscale code (0x800) for the ad5725 or zero code (0x000) for the ad5725-1. the clr to midscale code is most useful when the dac is configured for bipolar references and an output of 0 v is desired.
ad5725 rev. a | page 16 of 20 table 7. ad5725 logic truth table a1 a0 r/ w cs clr ldac input reg dac reg mode dac low low low low high low write write transparent a low high low low high low write write transparent b high low low low high low write write transparent c high high low low high low write write transparent d low low low low high high write hold write input a low high low low high high write hold write input b high low low low high high write hold write input c high high low low high high write hold write input d low low high low high high read hold read input a low high high low high high read hold read input b high low high low high high read hold read input c high high high low high high read hold read input d x x x high high low hold update all dac registers all x x x high high high hold hold hold all x x x x low x all registers set to mid/zero scale all x x x high x all registers latched to mid/zero scale all
ad5725 rev. a | page 17 of 20 power supplies power supplies required are av ss , av dd , and v l . the av ss supply can be set between ?15 v and 0 v. av dd is the positive supply; its operating range is between +5 v and +15 v. v l is the digital output supply voltage for the readback function. it is normally connected to +5 v. this pin is a logic reference input only. it does not supply current to the device. if the readback function is not used, v l can be left open-circuit. while v l does not supply current to the ad5725, it does supply current to the digital outputs when the readback function is used. reference configuration output voltage ranges can be configured as either unipolar or bipolar, and within these choices, a wide variety of options exists. the unipolar configuration can be either a positive or a negative voltage output, and the bipolar configuration can be either symmetrical or nonsymmetrical. adr01 +15 v input output trim 10k? +10v operation +15v ad5725 10f ?15v op1177 av dd av ss 0.1f v refp 0.2f v refn + 06442-007 figure 27. unipolar +10 v operation 0.2f ad5725 +15v 10f 0.1f +15 v ?15v av dd v refp v refn av ss balance 100k? gain 100k ? 4 6 12 5 13 8 3 1 14 15 7 6.2 ? 0.2f 6.2 ? 1f 39k ? ad688 for 10v ad588 for 5v 06442-008 5 or 10v operation figure 28. symmetrical bipolar operation figure 28 (symmetrical bipolar operation) shows the ad5725 configured for 10 v operation. see the ad688 data sheet for a full explanation of reference operation. adjustments may not be required for many applications since the ad688 is a very high accuracy reference. however, if additional adjustments are required, adjust the ad5725 full scale first. begin by loading the digital full-scale code (0xfff). then, adjust the gain adjust potentiometer to attain a dac output voltage of 9.9976 v. then, adjust the balance adjust to set the mid-scale output voltage to 0.000 v. the 0.2 f bypass capacitors shown at the reference inputs in figure 28 should be used whenever 10 v references are used. applications with single references or references to 5 v may not require the 0.2 f bypassing. the 6.2 resistor in series with the output of the reference amplifier is to keep the amplifier from oscillating with the capacitive load. we have found that this is large enough to stabilize this circuit. larger resistor values are acceptable, provided that the drop across the resistor does not exceed a v be . assuming a minimum v be of 0.6 v and a maximum current of 2.75 ma, the resistor should be under 200 for the loading of a single ad5725. using two separate references is not recommended. having two references can cause different drifts with time and temperature, whereas with a single reference, most drifts will track. unipolar positive full-scale operation can usually be set with a reference with the correct output voltage. this is preferable to using a reference and dividing down to the required value. for a 10 v full-scale output, the circuit can be configured as shown in figure 29 . in this configuration, the full-scale value is set first by adjusting the 10 k resistor for a full-scale output of 9.9976 v.
ad5725 rev. a | page 18 of 20 figure 29 shows the ad5725 configured for ?10 v to 0 v operation. an adr01 and op1177 are configured to produce a ?10 v output, which is connected directly to v refp for the reference voltage. single +5 v supply operation for operation with a +5 v supply, the reference voltage should be set between +1.0 v and +2.5 v for optimum linearity. figure 30 shows an adr03 used to supply a +2.5 v reference voltage. the headroom of the reference and dac are both sufficient to support a +5 v supply with 5 v tolerance. av dd and v l should be connected to the same supply. separate bypassing to each pin should be used. ad5725 0.2f 0v to ?10v operation u2 +15v ?15v ?15v u1 adr01 temp gnd +15v +15 v 10f 0.1f op1177 v+ v? v out v in trim av dd v refp v refn av ss 0 6442-009 5 v 10f 0.01f input output gnd trim 0.2f adr03 ad5725 10f 0.1f av dd av ss v refp v refn 0v to 2.5v operation single 5v supply 10k ? 06442-010 figure 29. unipolar ?10 v operation figure 30. +5 v sing le-supply operation
ad5725 rev. a | page 19 of 20 outline dimensions compliant to jedec standards mo-150-ah 060106-a 28 15 14 1 10.50 10.20 9.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 31. 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters ordering guide model temperature range inl (lsb) clear action package description package option ad5725arsz-1500rl7 1 ?40c to +85c 1 clear to zero scale 28-lead shrink small outline package [ssop] rs-28 ad5725arsz-1reel 1 ?40c to +85c 1 clear to zero scale 28-lead shrink small outline package [ssop] rs-28 ad5725arsz-500rl7 1 ?40c to +85c 1 clear to midscale 28-lead shrink small outline package [ssop] rs-28 ad5725arsz-reel 1 ?40c to +85c 1 clear to midscale 28-lead shrink small outline package [ssop] rs-28 ad5725brsz-1500rl7 1 ?40c to +85c 0.5 clear to zero scale 28-le ad shrink small outline package [ssop] rs-28 ad5725brsz-1reel 1 ?40c to +85c 0.5 clear to zero scale 28-le ad shrink small outline package [ssop] rs-28 AD5725BRSZ-500RL7 1 ?40c to +85c 0.5 clear to midscale 28-lead shrink small outline package [ssop] rs-28 ad5725brsz-reel 1 ?40c to +85c 0.5 clear to midscale 28-lead shrink small outline package [ssop] rs-28 1 z = rohs compliant part.
ad5725 rev. a | page 20 of 20 notes ?2007C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06442-0-12/08(a)

▲Up To Search▲

Price & Availability of AD5725BRSZ-500RL7

	To Download AD5725BRSZ-500RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .